A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

Author

Lee, S. ; Chae, J. ; Aniya, M. ; Takeuchi, S. ; Hamashita, K. ; Hanumolu, P.K. ; Temes, G.C.

Author_Institution

Sch. of EECS, Oregon State Univ., Corvallis, OR, USA

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a double-sampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process. The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.

Keywords

CMOS integrated circuits; adders; analogue-digital conversion; capacitors; distortion; wireless LAN; CMOS process; DAC capacitors; FoM; SFDR; SNR; THD; WLAN application; analog-to-digital converter; double-sampled low-distortion cascade ΔΣ modulator; embedded-adder integrator; gain 73.8 dB; gain 75.5 dB; gain 90.2 dB; loop-filter; low-distortion architecture; Bandwidth; Gain; Modulation; Quantization; Signal to noise ratio; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055289

Filename

6055289