A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and <;10ns read latency on a 45nm DRAM process. The architecture is based on small subarrays with short WL and BL to realize the low latency and energy efficiency. We also integrated several circuit techniques, including adaptive power to speed-up access time and banks rotation to reduce thermal issues. The proposed device is also estimated in a system simulation that shows that the power efficiency is higher than comparable systems.