3D stacked packages with bumpless interconnect technology

Novel 3D stacked packages fabricated with bumpless interconnect technology are presented. The single stacking unit can contain bare chips, packaged devices or passive components. An array of compliant terminals, or a series of copper pillars along the chip periphery are used as z-axis interconnects. To keep each single stacking unit thin, bumpless interconnect methods such as electro-chemical plating (ECP) or ball bonding are applied to connect the traces to the die pads directly. No wire bonding, lead-bond, solder bumps, substrate or vacuum sputtering films are involved. The traces route the pad to the z-axis interconnects (e.g., copper pillar, compliant terminal) which are orthogonal to the trace for 3D stacking assembly. Single stacking units are positioned in a vertical stack with their pillars and/or terminals aligned to one another. A single reflow operation simultaneously bonds all unit assemblies together to form the 3D stacked package. The compliant and deformable nature of solder paste and the routing traces provide flexible vertical interconnections that accommodate chips and packages with a wide range of thicknesses and sizes. The traces, pillars and/or compliant terminals serve as the interconnect matrix between the chips and packages, which may be functionally similar or different from one another, thereby increasing packaging density and functionality. Details of the design concepts, processing and the underlying bumpless interconnect technology are discussed along with key advantages and applications of these novel 3D stacked packages.