Title :
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
Author :
Cevrero, A. ; Aprile, C. ; Francese, P.A. ; Bapst, U. ; Menolfi, C. ; Braendli, M. ; Kossel, M. ; Morf, T. ; Kull, L. ; Yueksel, H. ; Oezkaya, I. ; Leblebici, Y. ; Cevher, V. ; Toifl, T.
Author_Institution :
IBM Res. - Zurich, Rueschlikon, Switzerland
Abstract :
This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7×8-tap cross decision-feedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER<; 10-12 with 12.5%UI margin. Itoccupies 300×350μm2 with an energy efficiency of 5.9mW/Gb/s.
Keywords :
CMOS integrated circuits; continuous time systems; crosstalk; decision feedback equalisers; interference suppression; radio receivers; silicon-on-insulator; FEXT cancellation circuits; Nyquist frequency; RX data-path; SOI CMOS; XCTLE; XDFE; channel bundle; cross continuous-time linear equalizer; direct feedback 7×8-tap cross decision-feedback equalizer; far-end crosstalk cancellation circuits; nearest aggressors; residual post-cursor FEXT; single-ended RX; single-ended channels; size 32 nm; Bit error rate; CMOS integrated circuits; Connectors; Crosstalk; Decision feedback equalizers; Latches;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231267
