Title :
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL
Author :
Park, Pyoungwon ; Park, Dongmin ; Cho, SeongHwan
Author_Institution :
Dept. of EE, KAIST, Daejeon, South Korea
Abstract :
A nested-PLL(NPLL) architecture for low-noise wide-bandwidth fractional-N frequency synthesizer is presented. In order to reduce the quantization noise of the fractional-N PLL, delta-sigma modulator(DSM) is clocked at nine times of the reference frequency. A band pass filter, implemented in form of a PLL, is added to reduce the noise folding. Prototype implemented in 0.13um CMOS process achieves 26dB quantization noise suppression while consuming 9.6mW and occupying 0.46mm2.
Keywords :
CMOS integrated circuits; delta-sigma modulation; frequency synthesizers; phase locked loops; quantisation (signal); CMOS process; band pass filter; high OSR delta-sigma modulator; low noise widebandwidth fractional-N frequency synthesizer; nested PLL; power 9.6 mW; quantization noise reduction; size 0.13 mum; Clocks; Frequency synthesizers; Phase locked loops; Phase noise; Quantization; Synthesizers;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055308
