12 Gbps GaAs 2-bit multiplexer/demultiplexer chip set for the SONET STS-192 system

Author

Ishida, K. ; Wakimoto, H. ; Yoshihara, K. ; Konno, M. ; Shimizu, S. ; Uchitomi, N. ; Toyoda, N.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

317

Lastpage

320

Abstract

Ultra-high-speed 2-b multiplexer (MUX) and demultiplexer (DEMUX) ICs have been developed for next-generation optical fiber communication systems in the SONET (synchronous optical network), which will require data bit rates of about 10 Gb/s. The ICs were fabricated using a 0.5- mu m WN/sub x/-gate process and were operated up to 12 Gb/s by adopting a tree-type architecture with a large phase margin and a new on-chip transmission line called the ladder grounded coplanar line. These ICs are applicable to future optical fiber communication systems (STS-192) as key devices.<>

Keywords

III-V semiconductors; multiplexing equipment; optical communication equipment; optical fibres; 0.5 micron; 12 Gbit/s; GaAs; SONET STS-192 system; WN/sub x/; data bit rates; ladder grounded coplanar line; multiplexer/demultiplexer chip set; on-chip transmission line; optical fiber communication systems; phase margin; synchronous optical network; tree-type architecture; Bit rate; Circuits; Clocks; Demultiplexing; FETs; Gallium arsenide; MESFETs; Multiplexing; Optical fiber communication; SONET;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69351

Filename

69351