Pre-project facility and layout planning for setting up cost effective wafer bumping processes

With the emergence of flip chip technologies in semiconductor assembly, a great deal of attention has been given to infrastructures such as wafer bumping services, equipment manufacturers, material and substrate suppliers. Little has been said about facility planning and design for flip chip processes. When rapid shifts in technology take place, optimum planning of facility layout is of great importance for productive manufacturing processes in term of cycle time, yield, quality control, and sustainability. This paper explores a facility layout design using Simplified Systematic Layout Planning (SSLP) techniques prior to the wafer bumping setup. Other techniques such as experiential, cloning, strategic or Bottom-up are difficult, if not impossible, to be applied in a process with new technological requirements. In this study, a "ball room" design is compared with "cellular" design by analyzing four basic elements: space planning units (SPUs), affinities, space, and constraints at the Macro-Space Plan level. The cellular layout arrangement is more cost effective than the ballroom design, however at the expense of its flexibility for future changes and upgrading. In this case, a low value-added space ratio is used to compensate the inflexibility. Differentiated cleanroom modules are designed for the sub-processes of wafer bumping so that the areas of high-grade cleanroom (ISO Class 5) are minimized. The final layout plan is further evaluated by using positive-negative-interesting (PNI) and material flow analysis (MFA) tools. In addition, special attention is paid to the integration of new and existing processes.