Improved circuits for microchip identification using SRAM mismatch

Author

Chellappa, Srivatsan ; Dey, Aritra ; Clark, Lawrence T.

Author_Institution

Sch. of Electr. Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

Integrated circuit authentication requires identification using un-clonable digital fingerprints. SRAM power-up state is one such fingerprinting method. In this paper we present a new, more robust hardware technique for generating secret keys and unique serial numbers using SRAM cells´ inherent mismatch due to process variations in the constituent transistors. The improved method can be used in operation and is amenable to devices using power-up BIST. It is experimentally demonstrated and analyzed on a 90 nm test chip.

Keywords

SRAM chips; built-in self test; transistors; SRAM cell inherent mismatch; SRAM power-up state; constituent transistor; integrated circuit authentication; microchip identification; power-up BIST; robust hardware technique; secret key generation; size 90 nm; unclonable digital fingerprint method; unique serial number; Fingerprint recognition; Integrated circuits; Inverters; Noise; Random access memory; Reliability; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055318

Filename

6055318