DocumentCode
1964697
Title
FPGA Implementation of an Adaptive Noise Canceller
Author
Lan, Tian ; Zhang, Jinlin
Author_Institution
Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Wuhan
fYear
2008
fDate
23-25 May 2008
Firstpage
553
Lastpage
558
Abstract
This paper proposes an FPGA implementation of an Adaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Spartan-3e Starter Kit as the target board. The experimental result of the hardware implementation shows the performance of LMS algorithm under different conditions and the feasibility of our architecture. A comparison between hardware and pure software implementation is then made with different filter taps.
Keywords
field programmable gate arrays; interference suppression; least mean squares methods; signal denoising; FPGA; Xilinx Spartan-3e starter kit; adaptive noise canceller; least mean square algorithm; Acoustic sensors; Adaptive filters; Application software; Digital signal processing; Field programmable gate arrays; Hardware; Least squares approximation; Noise cancellation; Signal processing algorithms; Very large scale integration; field programmable gate array (FPGA); hardware implementation; least mean square (LMS) filtering;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Processing (ISIP), 2008 International Symposiums on
Conference_Location
Moscow
Print_ISBN
978-0-7695-3151-9
Type
conf
DOI
10.1109/ISIP.2008.107
Filename
4554149
Link To Document