Fast and accurate event-driven simulation of mixed-signal systems with data supplementation

This paper presents a methodology of simulating behaviors of complex mixed-signal systems such as phase-locked loops (PLLs) and high-speed I/O interfaces on an event-driven HDL simulator like SystemVerilog. Continuous-time signal events as well as voltage and timing noises are accurately modeled without relying on fine time steps, based on a technique called data supplementation. That is, rather than representing a signal just as a series of time-value pairs, additional information is annotated using the struct construct in SystemVerilog. Prototype models for a 2-GHz PLL and a 2-Gbps high-speed series I/O system including a 2.9dB-loss channel at 1GHz demonstrate 50× and 80× faster simulation speeds, respectively, with the same or better accuracy compared with the conventional time-step based models.