Title :
A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer
Author :
Guowen Wei ; Shettigar, Pradeep ; Feng Su ; Xinyu Yu ; Kwan, Tom
Author_Institution :
Broadcom Corp., San Jose, CA, USA
Abstract :
A 13-ENOB, 5 MHz BW, 3.16 mW 3-bit continuous-time ΔΣ ADC sampling at 432 MHz is presented. For power efficiency, this design utilizes a hybrid feedback feed-forward loop topology with SAR quantizer, feed-forward compensated amplifiers, and push-pull DACs. Further power efficiency is gained by performing excess-loop-delay compensation (ELDC) using the SAR quantizer SC-DAC, which reduces power overhead from ELDC to a negligible level. A 94 dB SFDR is achieved through feedback-DAC calibration. The 0.066 mm2 design is fabricated in 28 nm CMOS and achieves FoMs of 36.4 fJ/step and 175.9 dB.
Keywords :
CMOS analogue integrated circuits; delta-sigma modulation; quantisation (signal); CMOS integrated circuit; SAR quantizer; analog-digital converter; continuous time delta-sigma ADC; excess-loop-delay compensation; feedback-DAC calibration; multibit delta-sigma ADC; power 3.16 mW; size 28 nm; successive approximation register; CMOS integrated circuits; Calibration; Filtering; Hybrid power systems; Linearity; Topology; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231295
