• DocumentCode
    1965094
  • Title

    Bottom-up digital system-level reliability modeling

  • Author

    Amador, N. Ruiz ; Huard, V. ; Pion, E. ; Cacho, F. ; Croain, D. ; Robert, V. ; Engels, S. ; Flatresse, P. ; Anghel, L.

  • Author_Institution
    Technol. R&D, STMicroelectron., Crolles, France
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.
  • Keywords
    integrated circuit modelling; integrated circuit reliability; digital system-level reliability modeling; gate-level models; transistor-level models; Degradation; Delay; Integrated circuit reliability; Logic gates; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055343
  • Filename
    6055343
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1965094