A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Author

Zimmer, Brian ; Yunsup Lee ; Puggelli, Alberto ; Kwak, Jaehwa ; Jevtic, Ruzica ; Keller, Ben ; Bailey, Stevo ; Blagojevic, Milovan ; Pi-Feng Chiu ; Hanh-Phuc Le ; Po-Hung Chen ; Sutardja, Nicholas ; Avizienis, Rimas ; Waterman, Andrew ; Richards, Brian ;

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA

fYear

2015

fDate

17-19 June 2015

Abstract

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Keywords

DC-DC power convertors; clocks; microprocessor chips; power aware computing; reduced instruction set computing; silicon-on-insulator; switched capacitor networks; FDSOI; RISC-V vector microprocessor; SC-DC-DC converters; Si; adaptive clocking; dynamic voltage scaling; fully-integrated noninterleaved switched-capacitor; on-chip voltages; simple packaging; size 28 nm; tightly integrated switched capacitor; voltage 0.5 V to 1 V; voltage 1.8 V; Adaptive systems; Clocks; Random access memory; Semiconductor device measurement; System-on-chip; Voltage control; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231305

Filename

7231305