A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic

Author

Inoue, Tomoo ; Izumi, Nobukazu ; Yoshikawa, Yuki ; Ichihara, Hideyuki

Author_Institution

Grad. Sch. of Inf. Sci., Hiroshima City Univ., Ozukahigashi, Japan

fYear

2010

fDate

13-15 Jan. 2010

Firstpage

345

Lastpage

349

Abstract

Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.

Keywords

VLSI; automatic test pattern generation; integrated circuit testing; integrated circuit yield; 16-valued logic system; 5-valued logic; VLSI testing; fast threshold test generation algorithm; fault acceptability; test pattern generation; yield enhancement; Algorithm design and analysis; Circuit faults; Circuit testing; Electronic equipment testing; Logic circuits; Logic design; Logic testing; System testing; Test pattern generators; Very large scale integration; 5-valued logic; PODEM; acceptable faults; error significance; threshold test generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on

Conference_Location

Ho Chi Minh City

Print_ISBN

978-0-7695-3978-2

Electronic_ISBN

978-1-4244-6026-7

Type

conf

DOI

10.1109/DELTA.2010.52

Filename

5438665