Title :
Three Dimensional integration - Considerations for memory applications
Author :
Iyer, S.S. ; Kirihata, T. ; Barth, J.E.
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY, USA
Abstract :
This paper reviews the technology and design considerations for the implementation of 3 Dimensional integration of memory in a high performance logic environment.
Keywords :
SRAM chips; integration; logic design; high performance logic environment; memory applications; three dimensional integration; Assembly; Copper; Integrated circuit interconnections; Laminates; Three dimensional displays; Through-silicon vias; Wiring; 3D EDA; 3D integration; TSVs; embedded memory;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055356
