Title :
A 14b 100MSample/s 3-stage A/D converter
Author :
Moreland, C. ; Elliott, M. ; Murden, F. ; Young, James ; Hensley, M. ; Stop, Russell
Author_Institution :
Analog Devices Inc., Greensboro, NC, USA
Abstract :
A 14b three-stage ADC uses a complementary bipolar process to achieve a 100MSample/s encode rate with a SFDR of >90 dB and an SNR of 75 dB. While the design is based on a traditional multi-stage architecture, the three encoder stages use serial-ripple converters. Unlike the typical N-bit flash converter which requires 2-/sup N-1/ comparators, the serial-ripple converter has only N comparators. The result is a smaller die area and lower power dissipation than flash. This design uses a total of 16 comparators, and at the full sample rate consumes 1250 mW. It is fabricated in a 0.8 /spl mu/m double-poly complementary bipolar process.
Keywords :
analogue-digital conversion; bipolar integrated circuits; comparators (circuits); low-power electronics; 0.8 micron; 1250 mW; 14 bit; SFDR; comparators; die area; double-poly complementary bipolar process; encode rate; multi-stage architecture; power dissipation; sample rate; serial-ripple converters; three-stage ADC; Circuit noise; Delay; Error correction; Hydrogen; Linearity; Noise reduction; Pipelines; Power dissipation; Resistors; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839679
