Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits

Summary form only given. Pass-transistor based circuits such as complementary pass-transistor logic (CPL) have recently emerged as strong contenders for implementation of high-performance arithmetic operations (Yano et al, 1996). The single-ended version known as LEAP offers the advantage of lower power in addition to high performance. The nMOS pass-transistor based circuits with partially-depleted SOI devices offer significant performance improvement over bulk-CMOS due to the absence of reverse body effects in the floating body configuration (thus minimising the V/sub T/ loss in passing the "high" state and improving the driving capability). This paper examines the effect of hysteretic V/sub T/ variation on the performance of LEAP and CPL circuits. The device used in this study has L/sub eff/=0.12 /spl mu/m, t/sub ox/=3.5 nm, t/sub Si/=200 nm, t/sub BOX/=400 nm, and the supply voltage (V/sub DD/) is 1.8 V.