Title :
A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz
Author :
Singer, L. ; Ho, S. ; Timko, M. ; Kelly, D.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Abstract :
A recent trend in cellular basestation design is to digitize multiple channels with a single ADC, often at the intermediate frequency (IF). This requires an ADC with wide dynamic range, particularly SFDR above 80 dB and SNR better than 70 dB, even when sampling input frequencies above 70 MHz. This 12b, 65MSample/s (MSPS) ADC incorporates a wide-bandwidth, low-distortion input stage coupled with a digitally-calibrated, multibit pipeline architecture optimized for low power consumption.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; 12 bit; 120 MHz; CMOS ADC; cellular basestation; digital calibration; intermediate frequency; low power operation; pipeline architecture; signal-to-noise ratio; spurious free dynamic range; Bandwidth; Broadband amplifiers; Calibration; Capacitors; Frequency; Linearity; Noise reduction; Pipelines; Sampling methods; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839681
