Title :
A 19 mW/lane Serdes transceiver for SFI-5.1 application
Author :
Fallahi, Siavash ; Cui, Delong ; Pi, Deyi ; Zhu, Rose ; Unruh, Greg ; Lugthart, Marcel ; Momtaz, Afshin
Author_Institution :
Broadcom® Corp., Irvine, CA, USA
Abstract :
A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.
Keywords :
CMOS integrated circuits; jitter; low-power electronics; radio transceivers; CMOS; SFI-5.1 application; Serdes transceiver; bit rate 3.125 Gbit/s; bit rate 50 Gbit/s; low power transceiver; power 19 mW; sinusoidal input jitter; small area transceiver; wavelength 40 nm; CMOS integrated circuits; Clocks; Finite impulse response filter; Jitter; Noise; Phase locked loops; Receivers; SFI-5.1; SerDes; transceivers and ADPLL;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055361
