A monolithic 3.125 Gbps fiber optic receiver front-end for POF applications in 65 nm CMOS

This paper describes the design of an analog receiver front-end targeting multi-gigabit data communications over large-core plastic optical fibers. A receiver front-end with an integrated photo detector has been implemented in a standard TSMC 65 nm low-power bulk-silicon CMOS process. A novel hybrid current buffer based transimpedance amplifier has been proposed to drive the 14 pF photo capacitance presented by the large-area photo detector to multi-gigahertz range. A digitally controlled slow-slope equalizer has also been integrated in the receiver front-end to compensate the high-frequency losses due to the integrated photo detector. The receiver front-end consumes 50 mW dc power from a 1.2 V supply (excluding output buffer) and achieves an NRZ data rate up to 3.125 Gbps.