Title :
A self-trimming 14b 100MSample/s CMOS DAC
Author :
Bugeja, A.R. ; Bang-Sup Song
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A 14b 100MSample/s CMOS DAC in 0.35 /spl mu/m CMOS achieves high static and dynamic linearity. The static linearity is obtained by a background self-trimming circuit which guarantees 14b INL/DNL. The dynamic linearity is obtained by the use of a track/attenuate stage at the DAC output. Maximum dynamic linearity is attained up to 100MSample/s update rate, but functionality is retained up to 200MSample/s. Power consumption from 3.3 V is 180 mW at 100MSample/s and 210 mW at 200MSample/s.
Keywords :
CMOS integrated circuits; digital-analogue conversion; low-power electronics; 0.35 micron; 14 bit; 180 to 210 mW; 3.3 V; CMOS; DAC; INL/DNL; background self-trimming circuit; dynamic linearity; functionality; power consumption; static linearity; track/attenuate stage; update rate; Calibration; Circuits; Current measurement; Energy consumption; Instruments; Linearity; Rails; Resistors; Switches; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839684
