A 0.6 W 10 Gb/s SONET/SDH bit-error-monitoring LSI

Author

Kawai, K. ; Ichino, H.

Author_Institution

NTT Network Innovation Labs., Kanagawa, Japan

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

54

Lastpage

55

Abstract

A low-power 10 Gb/s SONET/SDH monitoring LSI uses Si bipolar process. This is the first monitoring LSI operating at 10 Gb/s. The LSI monitors the bit errors in 10 Gb/s SONET/SDH frames using a parity byte B1. The LSI architecture is optimized for monitoring. The descrambler, which restores the incoming scrambled signal, is omitted to reduce power dissipation. The LSI can cope with 10 Gb/s and 2.5 Gb/s frame formats by using a multi-frame-format counter/decoder. The framer/demultiplexer is composed of a byte-aligning demultiplexer and a frame detector.

Keywords

SONET; bipolar digital integrated circuits; elemental semiconductors; large scale integration; low-power electronics; silicon; synchronous digital hierarchy; 0.6 W; 10 Gbit/s; SONET/SDH bit-error-monitoring LSI; Si; low-power Si bipolar IC; network fault management; Circuit faults; Clocks; Detectors; Large scale integration; Monitoring; Power dissipation; SONET; Synchronous digital hierarchy; Technological innovation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839688

Filename

839688