Title :
A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS
Author :
Lee, Chun C. ; Cho-Ying Lu ; Narayanaswamy, Ramya ; Rizk, Jad B.
Author_Institution :
Adv. Design, Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
A 12b 70MS/s sub-2 radix SAR ADC designed on Intel´s 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn´t require accurate references or input signals. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a novel preamplifier that helps achieve low-noise and high-speed operation. The ADC achieves 68.1dB SNDR, 80dB SFDR, 70MS/s speed, and consumes 4.3mW power.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; digital arithmetic; CMOS; SAR ADC; capacitor mismatches; digital startup calibration; power 4.3 mW; size 14 nm; sub-2 radix architecture; CMOS integrated circuits; CMOS process; Calibration; Capacitors; Preamplifiers; Redundancy;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231328
