Title :
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC
Author :
Zhijie Chen ; Miyahara, Masaya ; Matsuzawa, Akira
Author_Institution :
Tokyo Inst. of Technol., Tokyo, Japan
Abstract :
This paper presents an opamp-free solution to implement noise shaping in a successive approximation register analog-to-digital convertor. The comparator noise, incomplete settling error of digital-to-analog convertor and mismatch are alleviated. Designed in a 65 nm CMOS technology, the prototype realizes 58 dB SNDR at 50 MS/s sampling frequency. It consumes 120.7 μW from a 0.8 V supply and achieves a FoM of 14.8 fJ per conversion step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); digital-analogue conversion; CMOS technology; ENOB; FoM; SAR ADC; SNDR; comparator noise; digital-to-analog convertor; effective number of bits; noise-shaping; opamp-free solution; power 120.7 muW; size 65 nm; successive approximation register analog-to-digital convertor; voltage 0.8 V; CMOS integrated circuits; CMOS technology; Capacitors; Finite impulse response filters; Noise; Noise shaping; Prototypes; Charge redistribution; SAR ADC; noise shaping;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231329
