A simple and advanced neural circuit element by using an SOI insulated-gate pn junction device

Author

Omura, Y.

Author_Institution

Dept. of Electron., Kansai Univ., Osaka, Japan

fYear

1998

fDate

5-8 Oct. 1998

Firstpage

105

Lastpage

106

Abstract

Neural logic devices and circuits have been extensively studied, and recently, a /spl nu/MOS transistor and its logic circuits were proposed (Shibata and Ohmi, 1991). However, a /spl nu/MOS transistor which shows a neuron-like operation (sum of products) does not reflect a synaptic operation flexibly. The author has previously proposed a synaptic logic element by using an SOI insulated-gate p-n junction device called a lubistor (Omura, Appl. Phys. Lett. vol. 40, vol. 6, pp. 528-9, 1982), and recently demonstrated important functions (Omura, Ext. Abstr. of Int. Conf. on Solid State Dev. and Mat., pp. 140-1, 1997). This paper describes a new, simple, advanced neural circuit element and simulation results of circuit operations.

Keywords

circuit simulation; integrated circuit design; logic design; logic simulation; neural chips; p-n junctions; silicon-on-insulator; SOI insulated-gate p-n junction device; SOI insulated-gate p-n junction lubistor device; SOI insulated-gate pn junction device; Si-SiO/sub 2/; flexible synaptic operation; neural circuit element; neural circuit simulation; neural logic circuits; neural logic devices; neuron-like operation; nu-MOS transistor; nu-MOS transistor logic circuits; sum of products operation; synaptic logic element; Anodes; CMOS logic circuits; Circuit simulation; Insulation; Logic devices; Low voltage; MOSFETs; Pulse inverters; Voltage control; Weight control;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1998. Proceedings., 1998 IEEE International

Conference_Location

Stuart, FL, USA

ISSN

1078-621X

Print_ISBN

0-7803-4500-2

Type

conf

DOI

10.1109/SOI.1998.723133

Filename

723133