A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

Author

Li, Qingzheng ; Liang, Guixuan ; Bermak, Amine

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China

fYear

2010

fDate

13-15 Jan. 2010

Firstpage

207

Lastpage

211

Abstract

In this paper, a novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers. The proposed approach is demonstrated through a 0.18 Â¿m CMOS implementation of a 32-bit signed/unsigned multiplier. Reported results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.13 ns.

Keywords

CMOS logic circuits; VLSI; encoding; logic design; multiplexing equipment; pipeline processing; 32 bit signed pipelined multiplier; 32 bit unsigned pipelined multiplier; CMOS implementation; critical path delay; multiplexers; sign-control unit; unified implementation; Application software; Art; CMOS technology; Design engineering; Electronic equipment testing; Encoding; Energy consumption; Multiplexing; Signal processing algorithms; Silicon; Booth Encoding; Wallace Tree; fast adder; signed/unsigned multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on

Conference_Location

Ho Chi Minh City

Print_ISBN

978-0-7695-3978-2

Electronic_ISBN

978-1-4244-6026-7

Type

conf

DOI

10.1109/DELTA.2010.10

Filename

5438690