Title :
A 1 GHz Alpha microprocessor
Author :
Benschneider, B.J. ; Sungho Park ; Allmon, R. ; Anderson, W. ; Arneborn, M. ; Jangho Cho ; Changjun Ghoi ; Clouser, J. ; Sangok Han ; Hokinson, R. ; Gyoocheol Hwang ; Daesuk Jung ; Jaeyoon Kim ; Krause, J. ; Kwack, J. ; Meier, S. ; Yongsik Seok ; Thierauf
Author_Institution :
Compaq Comput. Corp., Shrewsbury, MA, USA
Abstract :
A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is highly leveraged from an existing 0.35 /spl mu/m, 6-way issue, 6 metal layer implementation with wire-bond packaging technology. The chip contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 kB 2-way set associative dual-ported data cache.
Keywords :
CMOS digital integrated circuits; VLSI; microprocessor chips; very high speed integrated circuits; 0.18 micron; 1 GHz; 64 kB; Al; Al interconnect layers; Alpha microprocessor; CMOS microprocessor; associative dual-ported data cache; associative instruction cache; custom VLSI implementation; flip-chip packaging; onchip cache arrays; Circuits; Diodes; Electronics packaging; Electrostatic discharge; Frequency estimation; Logic; Microprocessors; Routing; Variable structure systems; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839702
