A 660 MHz 64b SOI processor with Cu interconnects

Author

Buchholtz, T.C. ; Aipperspach, G. ; Cox, D.T. ; Phan, N.V. ; Storino, S.N. ; Strom, J.D. ; Williams, R.R.

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

88

Lastpage

89

Abstract

The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22 /spl mu/m SOI technology to a 0.18 /spl mu/m SOI technology. Key features of the 0.77 scaled 1.5 V technology are 0.08 /spl mu/m NFET channel lengths, 7 layer Cu metallization with low-/spl epsiv/ dielectric, low dose SOI substrate for improved material quality and productivity, and local interconnect. Dual gate oxide provides high I/O voltage compatibility. As this chip is a migration only 6 levels of metal and stacked devices for high voltage I/O were used.

Keywords

CMOS digital integrated circuits; copper; integrated circuit interconnections; microprocessor chips; reduced instruction set computing; silicon-on-insulator; very high speed integrated circuits; 0.08 micron; 1.5 V; 18 W; 64 bit; 660 MHz; CMOS SOI processor; CMOS8S2; Cu; Cu interconnects; Cu metallization; PowerPC RISC microprocessor; Si; dual gate oxide; high I/O voltage compatibility; low dose SOI substrate; Capacitance; Circuit noise; Clocks; Coupling circuits; Delay; Dielectric substrates; Frequency; Integrated circuit interconnections; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839703

Filename

839703