Simulation-based assessment of 50 nm double-gate SOI CMOS performance

Scaling CMOS to sub-0.1 /spl mu/m is a formidable task, irrespective of the particular technology. Bulk-Si devices require complex channel doping variations to control short-channel effects (SCEs). Partially depleted SOI devices also require such doping, and they involve additional design consideration of the (good and bad) floating-body effects. Conventional fully depleted (FD) SOI devices are scalable only to /spl sim/0.2 /spl mu/m. However, double-gate (DG) FD/SOI devices seem to be special; Monte Carlo simulations have shown them to have excellent characteristics at the lateral or 2D integration scaling limit of /spl sim/30 nm (Frank et al. IEEE IEDM Tech. Dig., p. 553, 1992). Ideally, the DG/SOI MOSFET, with the two gates electrically coupled through the thin SOI film, offers good control of SCEs even with uniform and very low film/channel doping, high drive current and transconductance due to the gate coupling and the inherent high carrier mobility, low off-current with low threshold voltage because of the nearly ideal subthreshold slope, and other unique features shown herein. The downside of DG/CMOS is the complex processing needed to fabricate the "near-ideal" devices. A poignant question then is how near ideal must the devices be for their unique features to significantly benefit real scaled circuits. In this paper, we provide insight to this question via a simulation-based study of 50 nm DG/SOI CMOS devices and circuits.