A new CMOS image sensor readout structure for 3D integrated imagers

This paper presents a new CMOS image sensor (CIS) structure and ADC design for three-dimensional (3D) integrated imagers. A modular design of CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (μbump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional decoding function achieves a high spatial resolution without degrading the frame rate performance. A 10b time-interleaved asynchronous successive approximation register (SAR) ADC was also implemented within 300 μm × 150 μm for array readout. A prototype chip with four sub-arrays (4×192×128 pixels) and a pixel size of 2.8×2.8 um² was fabricated using TSMC 0.18 um CIS process. The experimental results demonstrate the parallel output images of 4 modules successfully with 100fps. It shows that the array is expandable by modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications. The measured DNL, INL, and power consumption of the SAR ADC are +0.59/-0.41 LSB, +1.32/-0.73 LSB, and 130 μW respectively.