A 600 MHz 64 b PA-RISC microprocessor

Author

Hurd, K.A.

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

94

Lastpage

95

Abstract

This 64 b processor is a leveraged design based on the previous generation with the goal of a 1.2X performance increase on a short schedule in the same 5 metal layer, 0.25 /spl mu/m CMOS process. Speed path and clock tuning techniques increase the operating frequency. To reduce the cache miss rate, a quasi-least recently used (LRU) replacement algorithm is implemented using a LRU cache. The data cache on the quad issue processor is a 1 MB, dual ported, four way set associative design implemented on the die using 64 B per cache line.

Keywords

CMOS digital integrated circuits; cache storage; microprocessor chips; reduced instruction set computing; very high speed integrated circuits; 0.25 micron; 1 MB; 600 MHz; 64 bit; LRU cache; LRU replacement algorithm; PA-RISC microprocessor; cache miss rate reduction; clock tuning techniques; dual ported associative cache design; five metal layer CMOS process; four way set associative cache design; quad issue processor; quasi-least recently used replacement algorithm; speed path tuning techniques; Cache storage; Capacitance; Circuits; Clocks; Frequency; Logic; Microprocessors; Noise cancellation; Processor scheduling; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839706

Filename

839706