Energy-aware Filter Cache Architecture for Multicore Processors

Energy consumption as well as performance should be considered when designing high-performance multicore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential for high-performance multicore processors. In this paper, we propose new instruction cache architecture, which is based on the level-0 cache composed of filter cache and victim cache together, for multicore processors. The proposed architecture reduces the energy consumption in the instruction cache by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed technique reduces the energy consumption in the instruction cache by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.