Title :
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction
Author :
Ting-Kuei Kuan ; Shen-Iuan Liu
Author_Institution :
Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a digital bang-bang phase-locked loop that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. The chip is fabricated in a 40nm CMOS process. This bang-bang phase-locked loop achieves 290fsrms integrated jitter and reference spurs <;-72.89dBc. It consumes 3.8mW from a 1.1V supply while operating at 3.96GHz. This translates to an FOM of -245dB.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; CMOS integrated circuit; automatic loop gain control; digital bang-bang phase locked loop; frequency 3.96 GHz; jitter performance; loop latency reduction technique; power 3.8 mW; size 40 nm; voltage 1.1 V; Clocks; Gain control; Jitter; Noise; Phase locked loops; Semiconductor device measurement; Temperature measurement;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231354
