Sidelobe-Reduction Technique for Arrays with Block Phase Excitation

Block phase excitation in a large phased array reduces circuit complexity and system cost but results in high side lobes in certain directions. This paper introduces a technique for determining the locations and levels of the prominent sidelobes when each phase shifter is used to control the phase of two array elements in a linear array. A steepest-descent iterative procedure ure which minimizes the high sidelobes in an optimum manner is presented. Numerical examples are given.