Title :
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme
Author :
Moriwaki, Shinichi ; Kawasumi, Atsushi ; Suzuki, Toshikazu ; Sakurai, Takayasu ; Miyano, Shinji
Author_Institution :
Semicond. Technol. Acad. Res. Center (STARC), Yokohama, Japan
Abstract :
128kbit SRAM with charge share hierarchical bit line scheme has been fabricated in 65nm foundry technology. By transferring the data between local bit lines and global bit lines with charge sharing, the variation of bit line swing which causes wasted power consumption in low voltage operation has been suppressed. 3.3μw/MHz of power consumption at 0.4V is achieved.
Keywords :
SRAM chips; SRAM; bit line swing suppression charge; charge sharing; data transferring; foundry technology; hierarchical bit line scheme; power consumption; size 65 nm; storage capacity 128 Kbit; voltage 0.4 V; Capacitance; Computer architecture; Low voltage; Microprocessors; Monte Carlo methods; Power demand; Random access memory;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055398
