Designing a 5th order median filter with systolic array implementation

A median filter of order five implemented a as a systolic array is presented. The array consists of four different types of cells. Each of these cells introduces a half clock-cycle delay. In one-dimensional case a median filter slides a window on a stream of digital samples, sorts the samples into numerical order and outputs the dasiamedianpsila value that is the sample in the centre. Then, the window shifts one position on the incoming stream and the operation is repeated on the new set of samples every clock cycle. The schematic and layout of the chip was designed in electric version 8.05 using 0.18-micron TSMC technology. Simulation has been carried out in IRISM (v9.7). Inputs & outputs of the filter are 4-bit signed numbers in the range of -8 to +7.