Title :
Alleviating memory bottlenecks using multi-level memory
Author :
Dube, Deepak ; Von Mayrhauser, Anneliese
Author_Institution :
Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA
Abstract :
Limited primary memory and slow secondary memory device speeds are bottlenecks in many modern computer systems. They lead to drastic reduction in the throughput of such computer systems (thrashing) as the degree of multiprogramming (DMP) is increased. Alleviation of the problem by using a multilevel mass storage between the primary and the secondary memory systems is proposed. Analytic techniques applied to evaluate the proposal show that considerable performance gain can be obtained
Keywords :
many-valued logics; memory architecture; degree of multiprogramming; memory bottlenecks; multi-level memory; multilevel mass storage; performance gain; thrashing; Cache storage; Central Processing Unit; Computer science; Costs; Frequency; Information retrieval; Performance analysis; Performance gain; Proposals; Throughput;
Conference_Titel :
Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on
Conference_Location :
Charlotte, NC
Print_ISBN :
0-8186-2046-3
DOI :
10.1109/ISMVL.1990.122604
