Title :
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy
Author :
Okumura, Shunsuke ; Nakata, Yohei ; Yanagida, Koji ; Kagiyama, Yuki ; Yoshimoto, Shusuke ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Author_Institution :
Kobe Univ., Kobe, Japan
Abstract :
This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.
Keywords :
SRAM chips; low-power electronics; block-level instantaneous comparison feature; data comparison; dual modular redundancy; low-power 7T SRAM; power consumption; word length 1000000 bit; word length 16000 bit; word length 8000 bit; Bandwidth; Logic gates; Microprocessors; Power measurement; Program processors; Random access memory; Redundancy;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055411
