An integrated 2.5 GHz /spl Sigma//spl Delta/ frequency synthesizer with 5 /spl mu/s settling and 2 Mb/s closed loop modulation

Author

Wilingham, S. ; Perrott, M. ; Setterberg, B. ; Grzegorek, A. ; McFarland, B.

Author_Institution

Agilent Technol., Palo Alto, CA, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

200

Lastpage

201

Abstract

Three radio communication standards that share common performance requirements are gaining momentum. The 802.11 wireless LAN standard, the Bluetooth radio connectivity protocol, and the HomeRF SWAP home networking protocol all specify frequency hopping radios in the 2.4 GHz band using FSK modulation in a 1 MHz bandwidth. These standards require modest radio performance (compared to cellular systems), but demand small size and low cost. This paper describes a CMOS /spl Sigma//spl Delta/ fractional-N (/spl Sigma//spl Delta/FN) frequency synthesizer. In contrast to prior art, its 700 kHz bandwidth type-1 phase-locked loop (PLL) enables sub-5 /spl mu/s frequency hops plus 2- and 4-level digital Gaussian frequency shift keying (GFSK) modulation at 1 or 2 Mb/s.

Keywords

CMOS integrated circuits; frequency hop communication; frequency shift keying; frequency synthesizers; phase locked loops; sigma-delta modulation; 2 Mbit/s; 2.5 GHz; 5 mus; 700 kHz; CMOS sigma-delta fractional-N frequency synthesizer; closed loop modulation; digital Gaussian frequency shift keying modulation; frequency hopping radio communication; phase locked loop; settling time; Bandwidth; Bluetooth; Communication standards; Frequency shift keying; Frequency synthesizers; Phase locked loops; Radio communication; Spread spectrum communication; Wireless LAN; Wireless application protocol;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839748

Filename

839748