Threshold cancelling logic (TCL): a post-CMOS logic family scalable down to 0.02 /spl mu/m

Simple refrigeration of room-temperature-optimized CMOS devices does not enable low-voltage operation, because threshold voltage is higher at low temperatures. It might be possible to optimize threshold voltage for low-temperatures, but low-temperature-optimized CMOS suffers from a high leakage current at room temperature. This makes testing of the LSIs difficult. Burn-in testing with high temperature acceleration of feature modes would be particularly difficult because of the thermal runaway characteristics of the subthreshold current. This post-CMOS circuit family, threshold cancelling logic (TCL), can be scaled down to 0.02 /spl mu/m, corresponding to three generations smaller than conventional CMOS circuits.