Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling

In deep submicron processes, inaccuracy of interconnect models can lead to serious design errors. New circuit performance measurement schemes are necessary to verify and calibrate the interconnect models. An accurate in-situ noise and delay measurement technique is developed and a test chip is fabricated to demonstrate its efficacy. The proposed technique can experimentally characterize the noise peak height and the timing skew due to noise. It is intended for generating circuit design guidelines and verifying CAD models and tools.