An application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOS

This paper describes a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology. The methodology consists of following the components: compact models for device performance and reliability, compact models for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications. This approach is illustrated by applying it to the design of CMOS gate shrinks from 0.35 /spl mu/m to 0.29 /spl mu/m drawn poly gate length. The synthesized devices were manufactured, meeting all performance and reliability requirements in the first silicon run.