Title :
IC layout for an MOS neural type cell
Author :
Moon, G. ; Zaghloul, M.E. ; Newcomb, R.W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., Washington DC, USA
Abstract :
CMOS implementation of a neural-type cell (NTC) is described. Two MOS transistors are used to realize the linear resistors in the NTC. The integrated NTC simulation results verify the expected behavior of the cell. Several cells with different sizes have been designed and sent for fabrication
Keywords :
CMOS integrated circuits; neural nets; CMOS implementation; IC layout; MOS neural type cell; MOS transistors; linear resistor realisation; Biological system modeling; Circuit simulation; Fabrication; Hysteresis; Integrated circuit layout; MOSFETs; Mathematical model; Resistors; SPICE; Voltage control;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101896
