A LXI bus interfaces hardware design method with the SOPC

A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from Altera^TM was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.