A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation

A 8 b-wide single-ended simultaneous bidirectional transceiver test chip in a 0.4 /spl mu/m CMOS process allows study of the major challenges in high-performance, low-cost parallel-link design. This paper shows the I/O cell and placement of I/O pads in each chip. Data pins are laid out with different signal return configurations to study cross-talk in parallel links. In the I/O cell, the open-drain output driver is broken down into 4 legs ratioed 1:2:4:4 for swing control. The line is terminated on each side with a pMOS resistor, whose gate voltage is adjusted externally for impedance control. Two externally-adjustable reference voltages (VrefH and VrefL) are multiplexed to generate the local reference voltage (Vref) to decode incoming data. The I/O design operates at a bit time equal to 4 fanout-of-4 delays (FO4=delay of an inverter driving a load of 4 identical inverters and is 193 ps at a 3.3 V supply in this run). The bidirectional links operate at 2.4 Gb/s/pin (1.2 Gb/s in each direction), with 200 mV minimum signal swing on each side for the pins with worst-ease cross-talk.