A guide to simulation of hysteretic gate delays based on physical understanding [SOI logic]

Studies of floating body effects in SOI transistors and circuits have been widely reported. Nevertheless, in part because of the complexities of the device physics and the inaccuracies of numerical simulations, there is still need for a physical understanding of the floating body effect to guide a circuit designer in evaluation of the resulting hysteretic gate delay. This paper describes the dynamics of the floating-body effect in terms familiar to the circuit designer (voltages, capacitive coupling, and diode currents) and proposes a methodology for specification of body voltages for bounding circuit delay. This methodology is developed for inverters and can be extended to complex gates. A basis for detecting inaccuracies in SPICE simulations is included. Data showing the effect of drain-to-body capacitance on hysteretic behaviour is presented.