A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

Author

Takeda, K. ; Aimoto, Y. ; Nakamura, N. ; Toyoshima, H. ; Iwasaki, T. ; Noda, K. ; Matsui, K. ; Itoh, S. ; Masuoka, S. ; Horiuchi, T. ; Nakagawa, A. ; Shimogawa, K. ; Takahashi, H.

Author_Institution

NEC Corp., Sagamihara, Japan

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

264

Lastpage

265

Abstract

0.18 /spl mu/m logic process technologies have recently been used to develop a loadless CMOS four-transistor SRAM cell (4T-cell) whose size (1.934 /spl mu/m/sup 2/) is only 56% that of a conventional six-transistor SRAM cell (6T-cell). Using this 4T-cell technology. The authors present a 16 Mb, 400 MHz SRAM macro which features: (1) an end-point dual-pulse driver (EDD) for stable data hold and minimum cycle time, (2) word-line-voltage-level compensation (WLC) for stable static data hold, and (3) an all-adjoining twist bit-line (ATBL) to reduce bit-line coupling capacitance.

Keywords

CMOS memory circuits; SRAM chips; capacitance; circuit stability; compensation; high-speed integrated circuits; 0.18 micron; 16 Mbit; 400 MHz; SRAM cell; all-adjoining twist bit-line; bit-line coupling capacitance reduction; end-point dual-pulse driver; four-transistor SRAM macro; loadless CMOS SRAM macro; logic process technologies; stable data hold; word-line-voltage-level compensation; CMOS logic circuits; CMOS technology; Capacitance; Coupling circuits; FETs; Monitoring; National electric code; Random access memory; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839777

Filename

839777