VLSI implementations of neural-like networks for finite ring computations

An implementation procedure leading to a VLSI architecture of a finite ring neural-like network (FRNN) is developed. Techniques based on the concept of treating modulo reduction as a bit-level parallel neural-like network are introduced. The basic principle of the FRNN is introduced, and an architecture, together with a VLSI implementation, are proposed. A comparison is made with two existing techniques. It is shown that the FRNN approach produces much lower order of complexity for silicon area, while retaining throughput and latency complexities. An example of two different approaches to the implementation of a modulo adder are used to illustrate the material