A 0.4 /spl mu/m 3.3 V 1T1C 4 Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit

The charge distribution of memory cells is an important issue in high-density ferroelectric RAM (FRAM). Using memory cells as the reference cells provides an optimum reference voltage level, which automatically tracks the main memory cell properties. However, when memory cells are used as reference cells, the reference cells experience more access cycling than normal cells. Therefore, the endurance of the FRAM devices is determined by reference cells rather than by normal cells. Another issue is that, when the memory cells are used as reference cells, reference voltage level fluctuation cannot be avoided, especially in high-density FRAM, because variations of PZT film grain size and dimensions of the capacitor become serious. A variable reference bit line voltage scheme overcomes these problems. Unfortunately, the reference bit-line voltage scheme is not useful for all memory cells, because the reference voltage level is determined by a limited number of cells, not by all memory cells. This bit-line reference scheme is optimized with all of the memory cell charge information. Data protection is also used for unintentional power-off. An optimum read pulse width is suggested for high-speed FRAM.