Title :
A variable-frequency parallel I/O interface with adaptive power supply regulation
Author :
Gu-Yeon Wei ; Jaeha Kim ; Liu, D. ; Sidiropoulos, S. ; Horowitz, M.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
Adaptive power supply regulation reduces power dissipation in DSP and microprocessor cores. A technique extends this concept to a high-performance parallel input/output (I/O) interface. An inverter, used as the basic delay element in the core of a dual-loop delay-locked loop (DLL), has delay controlled by the supply voltage. This control voltage is replicated by a high-efficiency switching supply to power the rest of the interface and to maximize energy-efficient operation.
Keywords :
delay lock loops; digital signal processing chips; microprocessor chips; power supply circuits; DSP; adaptive power supply regulation; dual loop delay locked loop; energy efficiency; inverter; microprocessor; power dissipation; variable frequency parallel input-output interface; Circuit testing; Clocks; Delay; Frequency; Inverters; Power supplies; Regulators; Timing jitter; Transmitters; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839789
